Design of Priority Based Reconfigurable Router in Network on Chip

Abstract

Network on Chip (NoC) is an advanced integration design for communication networks and used as modules in System on Chip (SoC) designs. It provides the solution to the problem of traditional bus based SoC. A router is a key component which is considered as backbone of communication in NoC .The objective is to design a priority based reconfigurable router. Initially a 4x4 VLSI router is designed and synthesised, then the channels inside the router are modified to achieve reconfiguration in order to improve the efficiency of the router. In 4x4 Reconfigurable Router the slots are well utilized but prioritization was not considered. Since routers are associatedwith switches to take data transfer decisions and results in high power consumption. In order to overcome this problem, new priority based reconfigurable router is designed. The design entry for router is done using Verilog HDL, The design is synthesized and simulated using Xilinx ISE Design Suite 14.3 & ModelSim -Altera 6.5b software respectively and the corresponding results in terms of power and delay are analysed.