Informacije Midem-Journal of Microelectronics Electronic Components and Materials最新文献

英文中文

Towards smaller single-point failure-resilient analog circuits by use of a genetic algorithm 利用遗传算法实现更小的单点故障弹性模拟电路

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Informacije Midem-Journal of Microelectronics Electronic Components and Materials

Pub Date : 2023-10-10 DOI: 10.33180/infmidem2023.205

Failure-resilient analog circuits are difficult to design, but artificial intelligence can help crawl the topology solution space. Us-ing evolutionary computation-based topology synthesis we evolve analog arcus tangent computational circuits, resilient to any rectifying diode or resistor high-impedance single failure or removal. We encode analog circuit topologies as individuals with an upper-triangular incident matrix. Circuits are evolved using a combined technique utilizing parts of NSGA-II and PSADE, based on a special three-dimensional robustness function. We show that topology size for a failure-resilient circuit can be classes smaller than hand-made component-redundancy-based solutions. Our best failure-resilient topology comprises six diodes, three resistors, and a voltage offset source.

故障弹性模拟电路很难设计，但人工智能可以帮助抓取拓扑解决方案空间。使用基于进化计算的拓扑综合，我们进化出模拟弧切计算电路，对任何整流二极管或电阻高阻抗单故障或移除具有弹性。我们将模拟电路拓扑编码为具有上三角关联矩阵的个体。电路是基于特殊的三维鲁棒性函数，利用NSGA-II和PSADE部分的组合技术进行进化的。我们表明，故障弹性电路的拓扑尺寸可以比手工制作的基于组件冗余的解决方案小一些。我们最好的故障弹性拓扑结构包括六个二极管，三个电阻和一个电压偏移源。

引用次数: 0

A New Design Optimization Methodology of Fully Differential Dynamic Comparator 全差分动态比较器设计优化新方法

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Informacije Midem-Journal of Microelectronics Electronic Components and Materials

Pub Date : 2023-09-28 DOI: 10.33180/infmidem2023.204

The need to reduce time-to-market for high performances integrated circuits has become of primary concern in modern electronic design. Many efforts are currently spent to streamline the design process for increased complexity circuits while providing optimal performances, especially for nanoscale technologies. This paper presents a new and effective methodology for the design of fully differential comparators to achieve high performance operation using dynamic topology and nanoscale technology. The proposed methodology is not process dependent and can be applied to similar conventional comparator structures to optimize the speed operation while ensuring good offset cancellation, efficient noise immunity, and reduced design time and complexity. The design steps include theoretical analysis and simulation-based optimization of the comparator speed, as well as the offset and noise reduction within minimal design time. All the analog and digital building blocks are designed using dynamic topologies, including the clock generator, to ensure high speed and synchronized operation. The resulting circuit is a new two-stage dual clock fully differential comparator. Compared to its equivalent counterparts, it provides improved operation speed, and reduced offset voltage and kickback noise. This comparator is designed in TSMC 65 nm CMOS process. Its performances show that it achieves 1.25 GHz operation speed, presents less than 9 mV offset error, and generates a kickback noise less than 40 mV with a 10 kΩ input resistance during reset phase only. It consumes 213 µW from 1.2 V power supply at 1.25 GHz.

在现代电子设计中，需要缩短高性能集成电路的上市时间已成为主要关注的问题。许多努力目前花在简化设计过程，以增加复杂的电路，同时提供最佳的性能，特别是纳米技术。本文提出了一种利用动态拓扑和纳米尺度技术设计全差分比较器以实现高性能运行的新方法。所提出的方法不依赖于过程，可以应用于类似的传统比较器结构，以优化运行速度，同时确保良好的偏移抵消，有效的抗噪声，并减少设计时间和复杂性。设计步骤包括理论分析和基于仿真的比较器速度优化，以及在最小的设计时间内实现偏移和降噪。所有模拟和数字构建模块都使用动态拓扑设计，包括时钟发生器，以确保高速和同步操作。由此产生的电路是一种新型的两级双时钟全差分比较器。与同类产品相比，它提高了操作速度，降低了失调电压和反打噪声。该比较器采用台积电65nm CMOS工艺设计。结果表明，该系统工作速度达到1.25 GHz，失调误差小于9 mV，仅在复位阶段产生的反踢噪声小于40 mV，输入电阻为10 kΩ。在1.25 GHz时，从1.2 V电源消耗213µW。

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引用次数: 0

An Energy-efficient and Accuracy-adjustable bfloat16 Multiplier 一种节能且精度可调的bfloat16乘法器