Digitally Adjustable Differential Gain Stage

Abstract

Most ASIC’s demand signal conditioning sub-circuits to modify various signal parameters; one of the important parameter is the gain. The presented configuration is based on the conventional R-2R structure which mainly suffers from the mismatch imperfections. The study shows possible approach to improve mismatch characteristic or enables us to take the advantage to increase bit resolution without mismatch deteriorations. The approach could be used to even further improve accuracy of the numerous previously described approaches [1], [2] which already eliminate high resolution mismatch imperfections. Paper presents the implementation of the gain stage with digital gain adjustment, in the range from 0.9 to 1.1 in 128 equidistant monotonous steps, nevertheless the approach could be implemented even for higher resolution stages. For robust design in terms of the fabrication process and harsh environment operation, a fully differential amplifier was designed in standard 0.18μm CMOS technology. Designed amplifier in combination with resistive network is presented together with simulation results including the parasitic capacitances.