Design of CMOS On-Chip Transformer Coupled Matching Network for Millimeter-Wave Amplifiers with Optimal Chip Area

Abstract

Transformer coupled matching network is one of the alternative topologies for millimeter-wave integrated circuit design. Its impedance (inter-stage) transforming network (ITN) have been examined by planar and stacked topology with dimensional changing where planar transformer gives comparatively better performance than the stacked one. One-to-one-turn transformer-coupled ITN has been evaluated by the physical properties on optimum dimensional changing. Where ITN parameters and its properties function have been set below self-resonant frequencies (SRF) at 60 GHz & 79 GHz amplifiers. The quality factors (Qf)and insertion losses (IL)of transformer ITN are Qf@60GHz>20, insertion loss IL60GHz<4dB and Qf@79GHz>22, IL79GHz<3dB at their center frequency. Also, parasitic inter-winding capacitances between primary and secondary coil are minimum because of the phasor angle between these two-coil voltage goes near to 0°. At millimeter-wave, the parasitic resistances of transformer coupled ITN are coming down <3Ω form tee-type equivalent circuits of impedance matrices. Extracted Optimal values of capacitances, resistances and inductances help to increase mutual coupling coefficient as well as a good quality factor. Proposed planar and stacked small transformers have been utilized on ITN matching section of two millimeter-wave amplifiers on 55nm CMOS process. Supplying with 0.9V, mm-wave transformer coupled amplifiers have been designed layout area to 0.77 mm2 with 34.51 dB peak gain at 60 GHz and 0.46 mm2 with 17.15dB peak gain and both contain 24GHz 3dB bandwidth. As a result, it is confirmed that transformer coupled planar and modified stacked transformer are effective for shrinking layout area and high gain wideband 3dB BW in millimeter-wave regime.