{"title":"An 8.2 GHz triple coupling low-phase-noise class-F QVCO in 65nm CMOS","authors":"Haikun Jia, B. Chi, Zhihua Wang","doi":"10.1109/ESSCIRC.2015.7313844","DOIUrl":null,"url":null,"abstract":"An 8.2 GHz low-phase-noise Class-F quadrature voltage controlled oscillator (QVCO) is presented. With the proposed triple coupling technique, the oscillation frequency of the QVCO is only determined by the inter-stage passive matching components, and the introduced third harmonic at the drain of the transistors help form the approximately square voltage waveform to achieve low impulse-sensitivity function (ISF) value, which results in good phase noise performance and good quadrature phase accuracy. Implemented in 65nm CMOS, the QVCO shows a measured phase noise of -120.86 dBc/Hz at 1 MHz offset from 7.76 GHz carrier frequency (188.4 dBc/Hz FoM value), and a measured quadrature phase error of 0.72°. The QVCO consumes 10.6-12.3 mW power from one 0.6 V supply and 0.38mm2 active die area.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313844","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
An 8.2 GHz low-phase-noise Class-F quadrature voltage controlled oscillator (QVCO) is presented. With the proposed triple coupling technique, the oscillation frequency of the QVCO is only determined by the inter-stage passive matching components, and the introduced third harmonic at the drain of the transistors help form the approximately square voltage waveform to achieve low impulse-sensitivity function (ISF) value, which results in good phase noise performance and good quadrature phase accuracy. Implemented in 65nm CMOS, the QVCO shows a measured phase noise of -120.86 dBc/Hz at 1 MHz offset from 7.76 GHz carrier frequency (188.4 dBc/Hz FoM value), and a measured quadrature phase error of 0.72°. The QVCO consumes 10.6-12.3 mW power from one 0.6 V supply and 0.38mm2 active die area.