High-speed/low-power 1-D DWT architectures with high efficiency

Abstract

In this paper, we propose two scalable architecture's (called Arc/sub J/ and Arc*/sub 2/) which perform the Discrete Wavelet Transform (DWT) of an N/sub 0/-sample sequence in only N/sub 0//2 clock cycles. Therefore, they are at least twice as fast as the known architectures. Also, their AT/sup 2/ parameter is approximately 1/2 of that of already existing devices. These results allow either a twice faster processing than that allowed by other architectures working at the same clock frequency (High-Speed utilization), or using a twice lower clock frequency, while reaching the same performance as other architectures. This second possibility permits reducing the power dissipation by a factor of 4 with respect to other architectures (Low-Power utilization). Finally, we shall show that an impressively efficient architecture can be defined as the synthesis of Arc/sub J/ and Arc*/sub 2/ (average efficiency=99.1%, minimum efficiency=93.8%).