Y. Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, A. Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Y. Sakano, Y. Kitano, Takuya Nakamura, T. Toyama, H. Iwamoto, T. Ezaki
{"title":"An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure","authors":"Y. Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, A. Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Y. Sakano, Y. Kitano, Takuya Nakamura, T. Toyama, H. Iwamoto, T. Ezaki","doi":"10.1109/VLSIC.2016.7573543","DOIUrl":null,"url":null,"abstract":"A 4K2K 480 fps global-shutter CMOS image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 μVrms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of output image within 0.18 %. The 16-channel output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"148 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573543","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 40
Abstract
A 4K2K 480 fps global-shutter CMOS image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 μVrms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of output image within 0.18 %. The 16-channel output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
