A Robust Simulation Method for Breakdown with Voltage Boundary Condition Utilizing Negative Time Constant Information

Abstract

Dominant time constant analysis reveals that the semiconductor equations at hard breakdown turn into a positive feedback state where the convergence of steady state (DC) Newton iteration is substantially difficult even if continuation method is used. A robust simulation method for hard breakdown which detects the appearance of negative time constant during DC Newton iteration and then switches to transient (TR) simulation is proposed. The negative time constant value during the TR simulation is used for the time step restriction and the maximum time constant value is used for the determination of the final time of the TR simulation. By using the proposed method, a trace of the stable operation points in the snapback I-V trajectory corresponding to each DC bias can be obtained robustly with a simple voltage sweep at the voltage boundary.