Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication

D. Friedman, M. Meghelli, H. Ainspan, M. Soyuer
{"title":"Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication","authors":"D. Friedman, M. Meghelli, H. Ainspan, M. Soyuer","doi":"10.1109/VLSIC.2000.852870","DOIUrl":null,"url":null,"abstract":"Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10 Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5 GHz clock with 0.4 ps rms jitter synthesized from a /spl sim/195.3 MHz reference. The receive PLL (RxPLL), which exhibits <0.56 ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5 Gb/s input bit stream. The RxPLL operates error-free when tested with a 14 km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3 V are 270 mW and 330 mW, respectively.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"32 1","pages":"132-135"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852870","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

Abstract

Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10 Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5 GHz clock with 0.4 ps rms jitter synthesized from a /spl sim/195.3 MHz reference. The receive PLL (RxPLL), which exhibits <0.56 ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5 Gb/s input bit stream. The RxPLL operates error-free when tested with a 14 km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3 V are 270 mW and 330 mW, respectively.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
亚皮秒抖动SiGe BiCMOS发送和接收锁相环,用于12.5 Gbaud串行数据通信
完全集成的SiGe BiCMOS发送和接收锁相环,用于8B/10B编码的10gb /s串行链路,具有出色的抖动特性。发射PLL (TxPLL)提供一个12.5 GHz时钟,从一个/spl sim/195.3 MHz基准合成0.4 ps rms抖动。接收锁相环(RxPLL)显示<0.56 ps rms的抖动产生,提取全速率时钟并从12.5 Gb/s的输入比特流中恢复数据。RxPLL在14公里光链路试验台测试时无错误运行。3.3 V时TxPLL和RxPLL芯的功耗分别为270mw和330mw。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A translinear-based chip for linear LINC transmitters A 200 MHz, 3 mW, 16-tap mixed-signal FIR filter Sub 1-V 5-GHz-band up- and down-conversion mixer cores in 0.35-/spl mu/m CMOS A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs A wide-band direct conversion receiver with on-chip A/D converters
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1