Tilt angle effect on DC and AC performance of Halo PMOS

Abstract

Halo structure is usually adopted in deep submicron MOS devices for off-state leakage current reduction. Tilt angle of the Halo implant determines dopant distribution which gives anti-punchthrough operation. In this paper, we investigate the impact of tile angle on both DC and AC performance of Halo PMOS device via 2-D simulations. For DC performance, it is found that same conduction current is obtained for all tilt angles at same leakage current level. This performance equivalence can be traced back to a self compensation between body factor and source resistance, and implies that low tilt angle should be adopted for Halo devices, as it gives small threshold voltage and thus high noise margin. For AC performance, it is found that at same leakage current level, all tilt angles give same gate-to-drain capacitance and that lower tilt angle gives smaller drain-to-bulk junction capacitance.