An 8.865-GHz −244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique

S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu
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引用次数: 3

Abstract

This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.
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基于8.865 ghz−244dB-FOM高频压电谐振器的亚ppb级级分数n锁相环
本文提出了一种基于高频压电谐振器(PZR)的级联分数n锁相环,该锁相环采用亚ppb阶频率分辨率的通道调节技术,克服了使用窄幅GHz PZR的困难。此外,利用负电感技术抑制了互连线寄生电感引起的不良振荡。一个节能分频器有助于节省第二个锁相环的功率,抑制输出相位噪声的1ghz参考。原型锁相环采用65nm CMOS制造,输出为8.484GHz至8.912GHz, rmms抖动为180 fs, FOM为-244 dB,功耗为12.7mW。
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