S. Mathew, D. Johnston, P. Newman, Sudhir K. Satpathy, Vikram B. Suresh, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy
{"title":"μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS","authors":"S. Mathew, D. Johnston, P. Newman, Sudhir K. Satpathy, Vikram B. Suresh, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy","doi":"10.1109/ESSCIRC.2015.7313842","DOIUrl":null,"url":null,"abstract":"An all-digital full-entropy True Random Number Generator (TRNG) with measured 1.3GHz operation and total power consumption of 1.5mW at 0.75V, 25oC is fabricated in 14nm FinFET CMOS. Three independent self-calibrating entropy sources, coupled with pre-extraction correlation suppressors and a real-time BIW extractor enable ultra-low energy consumption of 3pJ/bit, while generating cryptographic-quality keys with measured Shannon entropy up to 0.99999999995 and lower-bound min-entropy >0.99. The 100% digital design enables a compact layout occupying 1088μm2, with scalable operation down to 300mV, while passing all NIST statistical randomness tests.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
An all-digital full-entropy True Random Number Generator (TRNG) with measured 1.3GHz operation and total power consumption of 1.5mW at 0.75V, 25oC is fabricated in 14nm FinFET CMOS. Three independent self-calibrating entropy sources, coupled with pre-extraction correlation suppressors and a real-time BIW extractor enable ultra-low energy consumption of 3pJ/bit, while generating cryptographic-quality keys with measured Shannon entropy up to 0.99999999995 and lower-bound min-entropy >0.99. The 100% digital design enables a compact layout occupying 1088μm2, with scalable operation down to 300mV, while passing all NIST statistical randomness tests.