Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers

Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, B. Hu, C. Wong, Mau-Chung Frank Chang
{"title":"Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers","authors":"Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, B. Hu, C. Wong, Mau-Chung Frank Chang","doi":"10.1109/VLSIC.2016.7573500","DOIUrl":null,"url":null,"abstract":"A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573500","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

Abstract

A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.
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用于环形振荡器I/Q接收机相位噪声消除的数字锁相环
提出了一种用于环形振荡器I/Q接收机的数字相位噪声消除技术。从数字锁相环(DPLL)中提取环形振荡器相位噪声,包括电源诱发的相位噪声,用于在数字域恢复随机旋转的基带信号。采用65nm CMOS技术制作的接收器原型在1MHz偏置时实现了相位噪声从-88到-109dBc/Hz的降低,在2.4GHz工作时实现了集成相位噪声(IPN)从-16.8到-34.6dBc的降低。
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