A 5.1mW 74dB DR CT ΔΣ modulator with quantizer intrinsic ELD compensation achieving 75fJ/conv.-step in a 20MHz BW

Abstract

A third-order continuous-time Delta-Sigma modulator in a 130 nm CMOS technology is presented. It features a 3-bit quantizer with an intrinsic excess loop delay compensation for half a clock cycle. The compensation is performed by means of adapting the reference voltages of the comparators on a sampling-to-sampling base, thus overcoming a power consuming summation of signals in front of the quantizer. Occupying merely 0.086mm2, the modulator achieves 66.4 dB SNDR and 74.6 dB DR in a 20 MHz bandwidth using a 640 MHz clock frequency. The power consumption equals 5.1 mW drawn from a 1.2 V supply voltage, which yields a state-of-the-art Walden figure of merit FOMW of 74.7 fJ/conv-step.