Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, W. Chan, J. Liaw, H. Liao, Jonathan Chang
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引用次数: 9
Abstract
A total solution for 8T dual-port (DP) SRAM to improve its operating voltage range (VMIN/VMAX) is proposed. Partial suppressed word-line (PSWL) technique improves the static noise margin (SNM) when both ports (A, B ports) access at the same time. Dummy read recovery (DRR) and negative bit-line (NBL) techniques are introduced to eliminate the dummy read induced write recovery failure and write contention failure, respectively. The silicon results show that the VDD operation window can be improved from 220mV to 570mV in 16nm FinFET technology.
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