A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS

Abstract

This paper describes design technique of energy-efficient ADC-DSP less sequence detection and equalization. This scheme takes advantage of the ISI in the channel to reconstruct the time domain bit sequence. This concept is demonstrated with a 4-bit sequence decoder designed and fabricated in 65nm CMOS using only 4-data, 3-edge comparators. Consuming only 35 mW at 10 Gb/s and without any transmit equalization, this receiver is capable of compensating 27 dB channel loss with 90 mV Voltage margin and 25 ps timing margin at BER of 10-12.