A 256-Mb Double-Data-Rate SDRAM with a 10-mW Analog DLL Circuit

Abstract

The developed 256-Mb double-data-rate (DDR) SDRAM employs a one-cycle stage-selection analog DLL (delayed-locked loop) circuit-running at IO mW with a 20-ps jitter and a 65- cycles lock-in - and a fully differential clocking system to provide 2~ 0.33-ns clock-to-data-output delay, 0.06-ns setup time and 0.26-ns hold time with respect to the data strobe. This performance represents the possibility of over 250-MHz (500 Mb/s/pin) operation. An even/odd-shared redundancy circuit for a 2-b prefetch reduces the number of fuses by 33%.