{"title":"用于模拟神经网络训练的CMOS电流模平方电路设计","authors":"Soyoun Park, Jae-Hee Lee, Hang-Geun Jeong, D. Im","doi":"10.1109/ISOCC50952.2020.9333090","DOIUrl":null,"url":null,"abstract":"We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 µm CMOS technology. The designed chip occupies a chip area of 408µm × 197µm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks\",\"authors\":\"Soyoun Park, Jae-Hee Lee, Hang-Geun Jeong, D. Im\",\"doi\":\"10.1109/ISOCC50952.2020.9333090\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 µm CMOS technology. The designed chip occupies a chip area of 408µm × 197µm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9333090\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9333090","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks
We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 µm CMOS technology. The designed chip occupies a chip area of 408µm × 197µm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.
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