用于分析沟槽DRAM结构的二维和三维泄漏现象

Proceedings of the 1991 International Conference on Microelectronic Test Structures Pub Date : 1990-03-18 DOI:10.1109/ICMTS.1990.161720

S. Voldman

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引用次数: 2

摘要

采用一组新颖的宏阵列沟槽DRAM(动态随机存取存储器)电容存储节点和平面MOS漏极结构，分析了中掺杂和重掺杂栅极二极管结构中的二维和三维泄漏现象。采用深掺杂门控二极管结构(沟槽型和平面型)，分析了栅致热机理和带间隧道效应。研究结果对于理解沟槽型DRAM和MOSFET漏极结构中的漏极现象具有重要意义

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Trench DRAM structures for the analysis of two- and three-dimensional leakage phenomena

Two- and three-dimensional leakage phenomena in moderately and heavily doped and gate diode structures are analyzed using a novel set of macro-array trench DRAM (dynamic random-access memory) capacitor storage nodes and planar MOS drain structures. Heavily doped gated diode structures (trench and planar) are used for the analysis of the gate-induced thermal generation mechanism and band-to-band tunneling. The results are relevant for understanding the leakage phenomena in trench DRAM and MOSFET drain structures.<>

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Proceedings of the 1991 International Conference on Microelectronic Test Structures

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