Mems内置自检使用MLS

A. Dhayni, S. Mir, L. Rufer
{"title":"Mems内置自检使用MLS","authors":"A. Dhayni, S. Mir, L. Rufer","doi":"10.1109/ETSYM.2004.1347607","DOIUrl":null,"url":null,"abstract":"This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for Micro Electro-Mechanical Systems (MEMS). The technique is based on Impulse Response (IR) evaluation using Maximum-Length Sequences (MLS). We will demonstrate the use of this technique and move forward to find the signature that is defined as the necessary samples of the impulse response needed to carry out an efficient test. We will use Monte-Carlo simulations to find the set of all fault-free devices under test (DUT). This set defines the impulse response space and the signature space. A DUT will be judged fault-free according to its signature being inside or outside the boundaries of the signature space. Finally, the test quality will be evaluated as function of the probabilities of false acceptance and false rejection, yield and percentage of test escapes. According to these test metrics, the design parameters (length of the MLS and the precision of the analogue to digital converter ADC) will be derived.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"352 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"Mems built-in-self-test using MLS\",\"authors\":\"A. Dhayni, S. Mir, L. Rufer\",\"doi\":\"10.1109/ETSYM.2004.1347607\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for Micro Electro-Mechanical Systems (MEMS). The technique is based on Impulse Response (IR) evaluation using Maximum-Length Sequences (MLS). We will demonstrate the use of this technique and move forward to find the signature that is defined as the necessary samples of the impulse response needed to carry out an efficient test. We will use Monte-Carlo simulations to find the set of all fault-free devices under test (DUT). This set defines the impulse response space and the signature space. A DUT will be judged fault-free according to its signature being inside or outside the boundaries of the signature space. Finally, the test quality will be evaluated as function of the probabilities of false acceptance and false rejection, yield and percentage of test escapes. According to these test metrics, the design parameters (length of the MLS and the precision of the analogue to digital converter ADC) will be derived.\",\"PeriodicalId\":358790,\"journal\":{\"name\":\"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.\",\"volume\":\"352 5\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ETSYM.2004.1347607\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETSYM.2004.1347607","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23

摘要

提出了一种微机电系统(MEMS)伪随机测试的内置自检(BIST)实现方法。该技术基于脉冲响应(IR)评估,使用最大长度序列(MLS)。我们将演示这种技术的使用,并继续寻找被定义为进行有效测试所需的脉冲响应的必要样本的签名。我们将使用蒙特卡罗模拟来找到所有被测无故障设备(DUT)的集合。这个集合定义了脉冲响应空间和签名空间。根据其签名在签名空间的边界内或边界外,判断被测对象是否无故障。最后,测试质量将作为错误接受和错误拒绝概率、产量和测试逃避百分比的函数进行评估。根据这些测试指标,推导出设计参数(MLS的长度和模数转换器ADC的精度)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Mems built-in-self-test using MLS
This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for Micro Electro-Mechanical Systems (MEMS). The technique is based on Impulse Response (IR) evaluation using Maximum-Length Sequences (MLS). We will demonstrate the use of this technique and move forward to find the signature that is defined as the necessary samples of the impulse response needed to carry out an efficient test. We will use Monte-Carlo simulations to find the set of all fault-free devices under test (DUT). This set defines the impulse response space and the signature space. A DUT will be judged fault-free according to its signature being inside or outside the boundaries of the signature space. Finally, the test quality will be evaluated as function of the probabilities of false acceptance and false rejection, yield and percentage of test escapes. According to these test metrics, the design parameters (length of the MLS and the precision of the analogue to digital converter ADC) will be derived.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Software development for an open architecture test system Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values Mems built-in-self-test using MLS A new BIST scheme for 5GHz low noise amplifiers Accurate tap-delay measurements using a di .erential oscillation technique
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1