{"title":"A hybrid FinFET/SOI MOSFET","authors":"W. Zhang, J. Fossum, L. Mathew","doi":"10.1109/SOI.2005.1563570","DOIUrl":null,"url":null,"abstract":"In this paper, process/physics-based generic compact model for DG MOSFETs, UFDG (Fossum, 2004), in Spice3, combined with simulations done with the 3D numerical simulator Davinci (2003), to gain insights regarding the design and performance of this hybrid device, which we call the inverted-T FET (ITFET) because of its cross-sectional shape we used. Based on UFDG/Spice3 simulations, we also note the potential benefit of the ITFET in effecting a good design of the FinFET-CMOS 6T-SRAM cell with regard to the area-performance tradeoff.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"2015 12","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563570","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
在本文中，基于工艺/物理的DG mosfet通用紧凑模型，UFDG (Fossum, 2004)，在Spice3中，结合三维数值模拟器Davinci(2003)的模拟，以获得关于这种混合器件的设计和性能的见解，我们称之为反t FET (ITFET)，因为我们使用了它的横截面形状。基于UFDG/Spice3模拟，我们还注意到ITFET在面积性能权衡方面对FinFET-CMOS 6T-SRAM单元的良好设计的潜在好处。
In this paper, process/physics-based generic compact model for DG MOSFETs, UFDG (Fossum, 2004), in Spice3, combined with simulations done with the 3D numerical simulator Davinci (2003), to gain insights regarding the design and performance of this hybrid device, which we call the inverted-T FET (ITFET) because of its cross-sectional shape we used. Based on UFDG/Spice3 simulations, we also note the potential benefit of the ITFET in effecting a good design of the FinFET-CMOS 6T-SRAM cell with regard to the area-performance tradeoff.
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