Characteristic Analysis of a Multi-chip Embedded Interposer Carrier using a Wafer-Level Fan-Out Process

In this paper, we investigated the structural analysis and electrical characteristics of EIC(Embedded Interposer Carrier) structure. The multi-chip EIC structure including a fan-out RDL process has been evaluated and developed. Key technologies including embedded interposers, molding process, temporary bonding, and RDL formation have been developed and integrated with good performance. The results indicate that the EIC carrier can be integrated, and there are data showing the feasibility of the chiplet in electronics applications. The electrical analysis will show not only frequency- and time-domain measurements under different lengths of interconnects but also the correlation between model and verification. In this new packaging structure, it is compatible with fan-out packaging technology and is easy to combine different chips to achieve performance close to 3D IC under a limited cost structure.