On the Static CMOS Implementation of Magnitude Comparators

Digital magnitude comparators are used in computer systems to compare two binary numbers and determine if these are equal, or if one number is greater or less than the other. In this work, a new magnitude comparator’s architecture is presented. The proposed comparator architecture is designed in static CMOS logic and compared against the state of the art magnitude comparators in the literature, shows less area overhead, and for small input operands (which are commonly used in practice) presents lower delay and power-delay product.