{"title":"fzcritical -一种基于新型模糊延迟模型的功能时序验证器","authors":"Rathish Jayabharathi, M. d'Abreu, J. Abraham","doi":"10.1109/ICVD.1999.745153","DOIUrl":null,"url":null,"abstract":"Chip performance and density are increasing tremendously and the CAD tools are always lagging behind. In this paper, we introduce a functional timing verifier using a novel fuzzy delay model which bridges the gap between the front-end timing verification and the back-end delay fault testing. The proposed fuzzy delay model can handle uncertainties with respect to timing characteristics, and manufacturing anomalies. Experimental results are presented for the ISCAS-85 benchmark circuits.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"FzCRITIC-a functional timing verifier using a novel fuzzy delay model\",\"authors\":\"Rathish Jayabharathi, M. d'Abreu, J. Abraham\",\"doi\":\"10.1109/ICVD.1999.745153\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip performance and density are increasing tremendously and the CAD tools are always lagging behind. In this paper, we introduce a functional timing verifier using a novel fuzzy delay model which bridges the gap between the front-end timing verification and the back-end delay fault testing. The proposed fuzzy delay model can handle uncertainties with respect to timing characteristics, and manufacturing anomalies. Experimental results are presented for the ISCAS-85 benchmark circuits.\",\"PeriodicalId\":443373,\"journal\":{\"name\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1999.745153\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FzCRITIC-a functional timing verifier using a novel fuzzy delay model
Chip performance and density are increasing tremendously and the CAD tools are always lagging behind. In this paper, we introduce a functional timing verifier using a novel fuzzy delay model which bridges the gap between the front-end timing verification and the back-end delay fault testing. The proposed fuzzy delay model can handle uncertainties with respect to timing characteristics, and manufacturing anomalies. Experimental results are presented for the ISCAS-85 benchmark circuits.
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