{"title":"基于随机存储器的加权脉冲神经网络模拟神经元设计","authors":"Chaeun Lee, Jaehyun Kim, Kiyoung Choi","doi":"10.1109/ISOCC47750.2019.9078507","DOIUrl":null,"url":null,"abstract":"Spiking neural networks (SNNs) are promising because they have the ability to represent signal strength information with a simple sequence of spikes having the same height. In this paper, we propose an RRAM-based analog neuron circuit for the weighted spiking neural network which is energy-efficient and hardware-friendly. We have designed the neuron circuit to show that the weighted spiking neural network can be implemented in analog and works properly.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network\",\"authors\":\"Chaeun Lee, Jaehyun Kim, Kiyoung Choi\",\"doi\":\"10.1109/ISOCC47750.2019.9078507\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Spiking neural networks (SNNs) are promising because they have the ability to represent signal strength information with a simple sequence of spikes having the same height. In this paper, we propose an RRAM-based analog neuron circuit for the weighted spiking neural network which is energy-efficient and hardware-friendly. We have designed the neuron circuit to show that the weighted spiking neural network can be implemented in analog and works properly.\",\"PeriodicalId\":113802,\"journal\":{\"name\":\"2019 International SoC Design Conference (ISOCC)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC47750.2019.9078507\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9078507","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network
Spiking neural networks (SNNs) are promising because they have the ability to represent signal strength information with a simple sequence of spikes having the same height. In this paper, we propose an RRAM-based analog neuron circuit for the weighted spiking neural network which is energy-efficient and hardware-friendly. We have designed the neuron circuit to show that the weighted spiking neural network can be implemented in analog and works properly.
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