高压CMOS工艺中嵌入可控硅的高鲁棒ESD保护结构

2008 IEEE International Reliability Physics Symposium Pub Date : 2008-07-09 DOI:10.1109/RELPHY.2008.4558959

T. Lai, M. Ker, W. Chang, Tien-Hao Tang, K. Su

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引用次数: 12

摘要

通过器件仿真研究了高压40 v CMOS工艺中HV mosfet器件结构和布局参数对ESD稳健性的影响，并在硅测试芯片上进行了验证。结果表明，在给定的40 v CMOS工艺中，将p型可控硅嵌入HV PMOS的新型ESD保护结构具有最高的ESD稳健性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.

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2008 IEEE International Reliability Physics Symposium

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