Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559010
C. Weulersse, A. Bougerol, G. Hubert, F. Wrobel, T. Carrière, R. Gaillard, N. Buard
This work shows the capabilities of Monte Carlo simulation based on nuclear database to identify the influence of device parameters and process on Single Cell Upset and Multicell Upset rates in integrated bulk and SOI CMOS technologies up to 65 nm. The method is applicable both to SRAM and logic cells, and is valid for high energy and thermal neutrons.
{"title":"Investigation of the influence of process and design on soft error rate in integrated CMOS technologies thanks to Monte Carlo simulation","authors":"C. Weulersse, A. Bougerol, G. Hubert, F. Wrobel, T. Carrière, R. Gaillard, N. Buard","doi":"10.1109/RELPHY.2008.4559010","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559010","url":null,"abstract":"This work shows the capabilities of Monte Carlo simulation based on nuclear database to identify the influence of device parameters and process on Single Cell Upset and Multicell Upset rates in integrated bulk and SOI CMOS technologies up to 65 nm. The method is applicable both to SRAM and logic cells, and is valid for high energy and thermal neutrons.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"73 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120874733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559002
H. Miura, K. Suzuki, T. Ikoma, S. Samukawa, H. Yoshikawa, S. Ueda
In this study, the degradation mechanism of dielectric properties of hafnium dioxide thin films was investigated by using quantum chemical molecular dynamics. Effects of point defects such as oxygen vacancies and carbon interstitials and residual stress in the films on their local band gap were analyzed quantitatively. Drastic decrease of the local band gap from about 5.7 eV to about 1.0 eV was caused by the formation of a defect-induced site in the band gap. Though this defect-induced site was recovered by additional oxidation, the remaining interstitial oxygen deteriorated the quality of the interface with tungsten electrode by forming new oxide between them. The estimated changes of the band gap and the interface structure were confirmed by experiments using synchrotron-radiation photoemission spectroscopy.
{"title":"Degradation of reliability of high-k gate dielectrics caused by point defects and residual stress","authors":"H. Miura, K. Suzuki, T. Ikoma, S. Samukawa, H. Yoshikawa, S. Ueda","doi":"10.1109/RELPHY.2008.4559002","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559002","url":null,"abstract":"In this study, the degradation mechanism of dielectric properties of hafnium dioxide thin films was investigated by using quantum chemical molecular dynamics. Effects of point defects such as oxygen vacancies and carbon interstitials and residual stress in the films on their local band gap were analyzed quantitatively. Drastic decrease of the local band gap from about 5.7 eV to about 1.0 eV was caused by the formation of a defect-induced site in the band gap. Though this defect-induced site was recovered by additional oxidation, the remaining interstitial oxygen deteriorated the quality of the interface with tungsten electrode by forming new oxide between them. The estimated changes of the band gap and the interface structure were confirmed by experiments using synchrotron-radiation photoemission spectroscopy.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121117541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559000
Y. Tai, Shih‐Che Huang, C. Chan
Poly-Si TFTs, which have the similar structures to the MOSFETs, are now having extensive studies for the applications in display system. The high device mobility of these devices enables the possibility to form both the in-pixel switches and integrated circuits with the poly-Si technology, which may greatly reduce the process complexity and fabrication cost. [1] Though recently several kinds of products formed with poly-Si technology had hit the market, the degradation mechanisms of the devices under dynamic operation with the drain biased are still not so clear. Y. Uraoka previously reported that the degradation behavior of the devices under gate AC operation with source/drain grounded is as a result of the swept carriers as the device is about to be turned off. [2] We have also reported that the degradation for the device operated in the off region as the source/drain grounded is because of the discharge behavior in the channel as the gate voltage toggling in the off region. [3] But these stress conditions are still far from the real operation conditions in applications. In this work, the degradation of the poly-Si TFTs under gate dynamic operation with drain biased, which would be much similar to the conditions operated in real applications, is carefully investigated.
{"title":"Characterization of device degradation of poly-Si TFTS under dynamic operation with drain biased","authors":"Y. Tai, Shih‐Che Huang, C. Chan","doi":"10.1109/RELPHY.2008.4559000","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559000","url":null,"abstract":"Poly-Si TFTs, which have the similar structures to the MOSFETs, are now having extensive studies for the applications in display system. The high device mobility of these devices enables the possibility to form both the in-pixel switches and integrated circuits with the poly-Si technology, which may greatly reduce the process complexity and fabrication cost. [1] Though recently several kinds of products formed with poly-Si technology had hit the market, the degradation mechanisms of the devices under dynamic operation with the drain biased are still not so clear. Y. Uraoka previously reported that the degradation behavior of the devices under gate AC operation with source/drain grounded is as a result of the swept carriers as the device is about to be turned off. [2] We have also reported that the degradation for the device operated in the off region as the source/drain grounded is because of the discharge behavior in the channel as the gate voltage toggling in the off region. [3] But these stress conditions are still far from the real operation conditions in applications. In this work, the degradation of the poly-Si TFTs under gate dynamic operation with drain biased, which would be much similar to the conditions operated in real applications, is carefully investigated.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124899325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559016
C. Guérin, V. Huard, C. Parthasarathy, J. Roux, A. Bravaix, E. Vincent
The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.
{"title":"Novel hot-carrier AC-DC design guidelines for advanced CMOS nodes","authors":"C. Guérin, V. Huard, C. Parthasarathy, J. Roux, A. Bravaix, E. Vincent","doi":"10.1109/RELPHY.2008.4559016","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559016","url":null,"abstract":"The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125950879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558866
J.P. Campbell, K. Cheung, J. Suehle, A. Oates
Recent negative bias temperature instability (NBTI) studies have come to involve very high electric fields, yet these same studies are used to criticize the lower field ldquoNBTIrdquo models. This study examines both high- and low-field degradation phenomena by monitoring the initial threshold voltage shift (DeltaVTH) as a function of stress time and stress voltage. We demonstrate that the initial DeltaVTH is recoverable and decays rapidly as the stress voltage is reduced. We also monitor the transient transconductance (GM) degradation which surprisingly indicates the presence of an electron trapping/de-trapping component. We argue that the initial DeltaVTH and GM degradation behaviors are consistent with high-field stress degradation. The electron trapping component of the ldquorecoverablerdquo degradation is unexpected and must be addressed to insure accurate NBTI lifetime predictions.
{"title":"The fast initial threshold voltage shift: NBTI or high-field stress","authors":"J.P. Campbell, K. Cheung, J. Suehle, A. Oates","doi":"10.1109/RELPHY.2008.4558866","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558866","url":null,"abstract":"Recent negative bias temperature instability (NBTI) studies have come to involve very high electric fields, yet these same studies are used to criticize the lower field ldquoNBTIrdquo models. This study examines both high- and low-field degradation phenomena by monitoring the initial threshold voltage shift (DeltaVTH) as a function of stress time and stress voltage. We demonstrate that the initial DeltaVTH is recoverable and decays rapidly as the stress voltage is reduced. We also monitor the transient transconductance (GM) degradation which surprisingly indicates the presence of an electron trapping/de-trapping component. We argue that the initial DeltaVTH and GM degradation behaviors are consistent with high-field stress degradation. The electron trapping component of the ldquorecoverablerdquo degradation is unexpected and must be addressed to insure accurate NBTI lifetime predictions.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115015659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558968
L. Scheick, L. Selva, Yuan Chen, L. Edmonds
The range of resulting leakage from single-event gate rupture (SEGR) in power MOSFETs spans several decades, from hundreds of nanoamps to tens of milliamps being qualified as rupture events. The differences in the magnitude of the breaks are correlated to the physical and operational effects of the devices investigated. The maximum leakage current that a part may endure and not destroy itself is determined experimentally and analytically.
{"title":"Current leakage evolution in partially gate-ruptured power MOSFETs","authors":"L. Scheick, L. Selva, Yuan Chen, L. Edmonds","doi":"10.1109/RELPHY.2008.4558968","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558968","url":null,"abstract":"The range of resulting leakage from single-event gate rupture (SEGR) in power MOSFETs spans several decades, from hundreds of nanoamps to tens of milliamps being qualified as rupture events. The differences in the magnitude of the breaks are correlated to the physical and operational effects of the devices investigated. The maximum leakage current that a part may endure and not destroy itself is determined experimentally and analytically.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115050897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558963
L. Lou, J. Liou
We have presented a comprehensive SCR compact model for CDM simulation. The work illustrated the useful and effective macromodeling approach of integrating the various industry standard models to describe the different devices imbedded in the SCR and treating the CDM-relevant operation states. In additional to the prediction of TLP results, the presented model demonstrates the effectiveness in analyzing CDM response of the I/O circuits and successfully explains why the input pins have lower CDM robustness than the output pins.
{"title":"Acomprehensive compact SCR model for CDM ESD circuit simulation","authors":"L. Lou, J. Liou","doi":"10.1109/RELPHY.2008.4558963","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558963","url":null,"abstract":"We have presented a comprehensive SCR compact model for CDM simulation. The work illustrated the useful and effective macromodeling approach of integrating the various industry standard models to describe the different devices imbedded in the SCR and treating the CDM-relevant operation states. In additional to the prediction of TLP results, the presented model demonstrates the effectiveness in analyzing CDM response of the I/O circuits and successfully explains why the input pins have lower CDM robustness than the output pins.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116172283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558856
G. Meneghesso, A. Tazzoli, F. A. Marino, M. Cordoni, P. Colombo
A new silicon controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 degC-125 degC). Using device simulation results , the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed.
{"title":"Development of a new high holding voltage SCR-based ESD protection structure","authors":"G. Meneghesso, A. Tazzoli, F. A. Marino, M. Cordoni, P. Colombo","doi":"10.1109/RELPHY.2008.4558856","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558856","url":null,"abstract":"A new silicon controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 degC-125 degC). Using device simulation results , the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122890419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558959
T. Lai, M. Ker, W. Chang, Tien-Hao Tang, K. Su
The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.
通过器件仿真研究了高压40 v CMOS工艺中HV mosfet器件结构和布局参数对ESD稳健性的影响，并在硅测试芯片上进行了验证。结果表明，在给定的40 v CMOS工艺中，将p型可控硅嵌入HV PMOS的新型ESD保护结构具有最高的ESD稳健性。
{"title":"High-robust ESD protection structure with embedded SCR in high-voltage CMOS process","authors":"T. Lai, M. Ker, W. Chang, Tien-Hao Tang, K. Su","doi":"10.1109/RELPHY.2008.4558959","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558959","url":null,"abstract":"The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114387655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559013
G. Du, D. Ang, Y.Z. Hu, S. Wang, C. Ng
Using an ultra-fast switching measurement method, the mechanism of NBTI recovery in the first few seconds after stress termination is systematically studied. Results show: (1) A component of the fast |DeltaVt| recovery increases with stress temperature; (2) the amount of |DeltaVt| recovery is (i) independent of stress time under a negative gate recovery voltage, but (ii) increases with stress time for a positive gate recovery voltage. These observations suggest the following physical framework for NBTI: (1) Dynamic balance of rapid inelastic trapping and detrapping of holes in a narrow energy band above Si valence band edge, which accounts for the fast recovery observed, independent of stress time and (2) generation of interface states and interfacial deep-level positive trap states (above Si mid-gap) which exhibit time-dependent recovery under a positive gate recovery voltage.
{"title":"Physical framework for NBTI: Insight from ultra-fast switching measurement of NBTI recovery","authors":"G. Du, D. Ang, Y.Z. Hu, S. Wang, C. Ng","doi":"10.1109/RELPHY.2008.4559013","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559013","url":null,"abstract":"Using an ultra-fast switching measurement method, the mechanism of NBTI recovery in the first few seconds after stress termination is systematically studied. Results show: (1) A component of the fast |DeltaVt| recovery increases with stress temperature; (2) the amount of |DeltaVt| recovery is (i) independent of stress time under a negative gate recovery voltage, but (ii) increases with stress time for a positive gate recovery voltage. These observations suggest the following physical framework for NBTI: (1) Dynamic balance of rapid inelastic trapping and detrapping of holes in a narrow energy band above Si valence band edge, which accounts for the fast recovery observed, independent of stress time and (2) generation of interface states and interfacial deep-level positive trap states (above Si mid-gap) which exhibit time-dependent recovery under a positive gate recovery voltage.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129529053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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