位串行MSPA体系结构的自动设计

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI:10.1109/ASPDAC.1995.486197

H. Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito

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引用次数: 1

摘要

存储器共享处理器阵列(MSPA)结构在数据存储和处理器单元利用率方面都是有效的。本文将MSPA的设计方法扩展到合成位串行数据路径。作为一个综合示例，我们提出了一种新的位串行乘法器，其逻辑门数量比传统的位串行乘法器少。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Automatic design for bit-serial MSPA architecture

A memory sharing processor array (MSPA) architecture is effective in both data storage and processor cell utilization efficiency. In this paper, the design methodology for MSPA is extended to synthesise a bit-serial datapath. As a synthesis example, we propose a new bit-serial multiplier with a smaller number of logic gates than conventional bit-serial multipliers.

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Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

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