{"title":"增强高性能可靠的AlSi/TiW金属化1.0 μ m CMOS工艺","authors":"H. Chou, W. Su, J.C. Liou, R. Shiue, H. Tuan","doi":"10.1109/vmic.1989.78061","DOIUrl":null,"url":null,"abstract":"Summary form only given. A reported AlSi/TiW metal system is developed with enhanced performance which is anticipated to upgrade the AlSi/TiW metallization. Standard VLSI process is followed for the contact formation process. Before the AlSi deposition, TiW is deposited and annealed using RTA, at a temperature ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively low temperature alloy is then adapted either by furnace or RTA. The average P+ contact resistance for a 1.2*1.2 mu m/sup 2/ contact is about 25 ohms as compared to 80 ohms for the conventional process. No junction degradation is observed at all for this higher temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C, 30 min. is twice as large as that for samples alloyed at 410 degrees C, 30 min. or 425 degrees C, 40 sec with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"166 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Enhanced high performance reliable AlSi/TiW metallization for 1.0 mu m CMOS process\",\"authors\":\"H. Chou, W. Su, J.C. Liou, R. Shiue, H. Tuan\",\"doi\":\"10.1109/vmic.1989.78061\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. A reported AlSi/TiW metal system is developed with enhanced performance which is anticipated to upgrade the AlSi/TiW metallization. Standard VLSI process is followed for the contact formation process. Before the AlSi deposition, TiW is deposited and annealed using RTA, at a temperature ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively low temperature alloy is then adapted either by furnace or RTA. The average P+ contact resistance for a 1.2*1.2 mu m/sup 2/ contact is about 25 ohms as compared to 80 ohms for the conventional process. No junction degradation is observed at all for this higher temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C, 30 min. is twice as large as that for samples alloyed at 410 degrees C, 30 min. or 425 degrees C, 40 sec with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<<ETX>>\",\"PeriodicalId\":302853,\"journal\":{\"name\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"volume\":\"166 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vmic.1989.78061\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vmic.1989.78061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Enhanced high performance reliable AlSi/TiW metallization for 1.0 mu m CMOS process
Summary form only given. A reported AlSi/TiW metal system is developed with enhanced performance which is anticipated to upgrade the AlSi/TiW metallization. Standard VLSI process is followed for the contact formation process. Before the AlSi deposition, TiW is deposited and annealed using RTA, at a temperature ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively low temperature alloy is then adapted either by furnace or RTA. The average P+ contact resistance for a 1.2*1.2 mu m/sup 2/ contact is about 25 ohms as compared to 80 ohms for the conventional process. No junction degradation is observed at all for this higher temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C, 30 min. is twice as large as that for samples alloyed at 410 degrees C, 30 min. or 425 degrees C, 40 sec with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<>