一个10位高速CMOS CAS宏单元

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56703

A. W. Vogt, I. Dedic

{"title":"一个10位高速CMOS CAS宏单元","authors":"A. W. Vogt, I. Dedic","doi":"10.1109/CICC.1989.56703","DOIUrl":null,"url":null,"abstract":"A 10-bit 50 M-sample/s digital-to-analog converter has been fabricated in a 3-μm, double-metal, single-polysilicon CMOS process. The architecture of the converter was chosen to minimize the effects of chip gradients, mismatches and transistor parameters, voltage drops in supply tracks, and other nonideal effects. Close attention was paid to the dynamic behavior of the converter to reduce output glitches and code-dependent distortion","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 10-bit high speed CMOS CAS macrocell\",\"authors\":\"A. W. Vogt, I. Dedic\",\"doi\":\"10.1109/CICC.1989.56703\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit 50 M-sample/s digital-to-analog converter has been fabricated in a 3-μm, double-metal, single-polysilicon CMOS process. The architecture of the converter was chosen to minimize the effects of chip gradients, mismatches and transistor parameters, voltage drops in supply tracks, and other nonideal effects. Close attention was paid to the dynamic behavior of the converter to reduce output glitches and code-dependent distortion\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56703\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56703","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

采用3 μm双金属单多晶硅CMOS工艺制备了10位50 m采样/s数模转换器。转换器的结构选择是为了最小化芯片梯度、错配和晶体管参数、电源轨道电压降和其他非理想效应的影响。密切关注转换器的动态行为，以减少输出小故障和码相关失真

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 10-bit high speed CMOS CAS macrocell

A 10-bit 50 M-sample/s digital-to-analog converter has been fabricated in a 3-μm, double-metal, single-polysilicon CMOS process. The architecture of the converter was chosen to minimize the effects of chip gradients, mismatches and transistor parameters, voltage drops in supply tracks, and other nonideal effects. Close attention was paid to the dynamic behavior of the converter to reduce output glitches and code-dependent distortion

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

自引率

0.00%

发文量

期刊最新文献

A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array A gate matrix deformation and three-dimensional maze routing for dense MOS module generation A submicron CMOS triple level metal technology for ASIC applications Hot carrier effects on CMOS circuit performance The QML-an approach for qualifying ASICs