利用喷涂和角度暴露技术在垂直壁面上形成导电图案的方法

H. Morii, F. Oohira, M. Sasaki, T. Ochi, A. Yuzuriha
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引用次数: 2

摘要

提出了一种利用抗蚀剂喷涂和角度暴露技术在垂直壁上形成导电图案的新方法。这种方法使减小芯片封装尺寸成为可能。所述喷涂和角度暴露技术使抗蚀剂涂层均匀,并使抗蚀剂在600 mm高度的垂直壁上形成图案。然后溅射导电图案层并进行化学镀。结果表明,在垂直壁面上成功地形成了宽度为200 μ m、间距为300 μ m的导电图案。
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Conductive pattern forming method on vertical wall using spray coating and angled exposure technologies
A novel conductive pattern forming method on the vertical wall using a resist spray coating and an angled exposure technologies is proposed. This method makes it possible to decrease the chip package size. The spray coating and the angled exposure technologies enable the uniform resist coating and the patterning the resist on the vertical wall of 600 mum height. Then a conductive pattern layers are sputtered and electroless plated. As the result, the conductive patterns of 200 mum width and 300 mum spacing is successfully formed on the vertical walls.
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