Dual-section-average (DSA) analog-to-digital converter (ADC) in digital pulse width modulation (DPWM) DC-DC converter for reducing the problem of limiting cycle

This paper proposes a dual-section average (DSA) analog-to-digital converter (ADC) to achieve a closed-loop digital pulse width modulation (DPWM) DC-DC converter with performance compatible to that by the analog PWM converter. For a 2.4 V input voltage, a regulated output voltage of 1.2 V can provide output current of 600 mA without any off-chip compensators. Besides, the output ripple can be reduced to about 8 mVp-p by theoretical result. The test chip was fabricated in 0.35 mum CMOS technology. Owing to the parasitic resistance, the output ripple of the experimental result is within 8 mVp-p. Furthermore, the transient recovery time is within 50 mus when load current changes from 120 mA to 600 mA, or vice versa.