VHDL中的同步设计

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410681

A. Debreil, P. Oddo

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引用次数: 10

摘要

此前，作者(Proc. Euro;设计自动售货机。Conf.， pp. 680-681, 1992)定义了如何将同步设计的概念映射到VHDL描述。现在，它们提出了一组规则，如果遵守这些规则，VHDL描述就是同步的。然后，他们将严格的同步概念扩展到可以重新同步的电路，假设具有良好的定时特性，并为此目的引入清洁度的概念。

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Synchronous designs in VHDL

Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming some good timing property and introduce the concept of cleanliness for this purpose.<>

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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