Towards simultaneous delay-fault built-in self-test and partial-scan insertion

We propose a novel hardware model to reconfigure a sequential ULSI circuit for partial-scanned delay-fault built-in self-test (BIST). We modify the standard stuck-fault BIST model to ensure highly robust delay tests by inserting hardware to avoid circuit hazards that invalidate delay tests. The model treats un-scanned flip-flops and latches as inverters or buffers. We propose a novel minimum feedback vertex set (FVS) algorithm based on quadratic 0-1 programming (which has O(n/sup 2/) complexity) for partial-scan flip-flop selection. We obtain a pipelined sequential circuit and insert parity-flippers to remove hazards during testing. We avoid placing hardware on time-critical paths. We find the FVS and insert deglitching hardware for all of the 1989 ISCAS circuits.