{"title":"用Petri网模型分析多进程VHDL规范","authors":"J. Muller, H. Kramer","doi":"10.1109/EURDAC.1993.410679","DOIUrl":null,"url":null,"abstract":"A method for analyzing behavioral multiprocess VHDL specifications used for optimizing system-level synthesis is presented. To determine the access conflicts to the global data signals, the system behavior must be analyzed. Therefore the synchronization scheme is modeled as a Petri net, which can be minimized by transformation. A reduced case graph is regarded as a state transition graph of the system states. To calculate the probabilities of the access conflicts, the probability of observing the system in a certain state must be determined. This is done by calculation of the stationary distribution of a Markov chain.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Analysis of multi-process VHDL specifications with a Petri net model\",\"authors\":\"J. Muller, H. Kramer\",\"doi\":\"10.1109/EURDAC.1993.410679\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A method for analyzing behavioral multiprocess VHDL specifications used for optimizing system-level synthesis is presented. To determine the access conflicts to the global data signals, the system behavior must be analyzed. Therefore the synchronization scheme is modeled as a Petri net, which can be minimized by transformation. A reduced case graph is regarded as a state transition graph of the system states. To calculate the probabilities of the access conflicts, the probability of observing the system in a certain state must be determined. This is done by calculation of the stationary distribution of a Markov chain.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410679\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410679","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis of multi-process VHDL specifications with a Petri net model
A method for analyzing behavioral multiprocess VHDL specifications used for optimizing system-level synthesis is presented. To determine the access conflicts to the global data signals, the system behavior must be analyzed. Therefore the synchronization scheme is modeled as a Petri net, which can be minimized by transformation. A reduced case graph is regarded as a state transition graph of the system states. To calculate the probabilities of the access conflicts, the probability of observing the system in a certain state must be determined. This is done by calculation of the stationary distribution of a Markov chain.<>
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