{"title":"神经形态半导体存储器","authors":"C. Lam","doi":"10.1109/3DIC.2015.7334566","DOIUrl":null,"url":null,"abstract":"Microprocessors designed with von Neumann architecture are hitting the power and performance limits as silicon CMOS continues to scale the critical dimensions of the circuit components towards single digit nanometer size limit. Multi-core processor, parallel processing without increasing operating frequency of the cores, was introduced in the early 2000 to extend the power and performance scaling, keeping Moore's Law viable. Evolution has provided us with the most efficient parallel processing architecture: the biological brain. In this talk, we shall examine what we can do with little that we know about how the brain works to design machines to mimic the brain's memory.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Neuromorphic semiconductor memory\",\"authors\":\"C. Lam\",\"doi\":\"10.1109/3DIC.2015.7334566\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Microprocessors designed with von Neumann architecture are hitting the power and performance limits as silicon CMOS continues to scale the critical dimensions of the circuit components towards single digit nanometer size limit. Multi-core processor, parallel processing without increasing operating frequency of the cores, was introduced in the early 2000 to extend the power and performance scaling, keeping Moore's Law viable. Evolution has provided us with the most efficient parallel processing architecture: the biological brain. In this talk, we shall examine what we can do with little that we know about how the brain works to design machines to mimic the brain's memory.\",\"PeriodicalId\":253726,\"journal\":{\"name\":\"2015 International 3D Systems Integration Conference (3DIC)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International 3D Systems Integration Conference (3DIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/3DIC.2015.7334566\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC.2015.7334566","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Microprocessors designed with von Neumann architecture are hitting the power and performance limits as silicon CMOS continues to scale the critical dimensions of the circuit components towards single digit nanometer size limit. Multi-core processor, parallel processing without increasing operating frequency of the cores, was introduced in the early 2000 to extend the power and performance scaling, keeping Moore's Law viable. Evolution has provided us with the most efficient parallel processing architecture: the biological brain. In this talk, we shall examine what we can do with little that we know about how the brain works to design machines to mimic the brain's memory.