D. Heidel, S. Dhong, H. P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz
{"title":"用于评估1ghz微处理器的高速串行/反串行测试设计方法","authors":"D. Heidel, S. Dhong, H. P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz","doi":"10.1109/VTEST.1998.670873","DOIUrl":null,"url":null,"abstract":"As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor\",\"authors\":\"D. Heidel, S. Dhong, H. P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz\",\"doi\":\"10.1109/VTEST.1998.670873\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.\",\"PeriodicalId\":128521,\"journal\":{\"name\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1998.670873\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1998.670873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor
As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.