M. Horiuchi, T. Teshima, K. Tokumasu, K. Yamaguchi
{"title":"高电流、小寄生电容mosfet在多晶硅层间(PSI: /spl PSI /) SOI晶圆上","authors":"M. Horiuchi, T. Teshima, K. Tokumasu, K. Yamaguchi","doi":"10.1109/VLSIT.1995.520846","DOIUrl":null,"url":null,"abstract":"An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer\",\"authors\":\"M. Horiuchi, T. Teshima, K. Tokumasu, K. Yamaguchi\",\"doi\":\"10.1109/VLSIT.1995.520846\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520846\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer
An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.