J. Uehlin, W. A. Smith, V. R. Pamula, S. Perlmutter, V. Sathe, J. Rudell
{"title":"基于标准65nm CMOS的64通道记录、共振刺激和伪影抑制的双向脑机接口","authors":"J. Uehlin, W. A. Smith, V. R. Pamula, S. Perlmutter, V. Sathe, J. Rudell","doi":"10.1109/ESSCIRC.2019.8902911","DOIUrl":null,"url":null,"abstract":"A single-chip bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This paper presents a prototype BBCI ASIC including a 64-channel time-multiplexed recording front-end, 4-channel high-voltage compliant resonant-stimulator and electronics to support concurrent multi-channel differential- and common-mode stimulus artifact cancellation. A cascaded charge pump-based stimulation driver provides +/-11V compliance using 1.2V devices. High-frequency (~3GHz), self-resonant clocking is used to reduce capacitor area while suppressing associated switching losses. A 32-tap LMS-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip is powered by 2.5/1.2V supplies, dissipating 205µW in recording, 142µW in the cancellation back-end, and 31% DC-DC efficiency in the stimulation drivers, each with a maximum output power of 24mW. This 4mm2 neural interface chip was implemented in 65nm 1P9M LP CMOS.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS\",\"authors\":\"J. Uehlin, W. A. Smith, V. R. Pamula, S. Perlmutter, V. Sathe, J. Rudell\",\"doi\":\"10.1109/ESSCIRC.2019.8902911\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-chip bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This paper presents a prototype BBCI ASIC including a 64-channel time-multiplexed recording front-end, 4-channel high-voltage compliant resonant-stimulator and electronics to support concurrent multi-channel differential- and common-mode stimulus artifact cancellation. A cascaded charge pump-based stimulation driver provides +/-11V compliance using 1.2V devices. High-frequency (~3GHz), self-resonant clocking is used to reduce capacitor area while suppressing associated switching losses. A 32-tap LMS-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip is powered by 2.5/1.2V supplies, dissipating 205µW in recording, 142µW in the cancellation back-end, and 31% DC-DC efficiency in the stimulation drivers, each with a maximum output power of 24mW. This 4mm2 neural interface chip was implemented in 65nm 1P9M LP CMOS.\",\"PeriodicalId\":402948,\"journal\":{\"name\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2019.8902911\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902911","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS
A single-chip bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This paper presents a prototype BBCI ASIC including a 64-channel time-multiplexed recording front-end, 4-channel high-voltage compliant resonant-stimulator and electronics to support concurrent multi-channel differential- and common-mode stimulus artifact cancellation. A cascaded charge pump-based stimulation driver provides +/-11V compliance using 1.2V devices. High-frequency (~3GHz), self-resonant clocking is used to reduce capacitor area while suppressing associated switching losses. A 32-tap LMS-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip is powered by 2.5/1.2V supplies, dissipating 205µW in recording, 142µW in the cancellation back-end, and 31% DC-DC efficiency in the stimulation drivers, each with a maximum output power of 24mW. This 4mm2 neural interface chip was implemented in 65nm 1P9M LP CMOS.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
