{"title":"全芯片开关噪声分析的分层电源分布模型","authors":"H.H. Chen","doi":"10.1109/EPEP.1997.634039","DOIUrl":null,"url":null,"abstract":"This paper describes the use of a 12/spl times/12 SCM power supply distribution model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A hierarchical power supply distribution model for full-chip switching noise analysis\",\"authors\":\"H.H. Chen\",\"doi\":\"10.1109/EPEP.1997.634039\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the use of a 12/spl times/12 SCM power supply distribution model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.\",\"PeriodicalId\":220951,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.1997.634039\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.1997.634039","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A hierarchical power supply distribution model for full-chip switching noise analysis
This paper describes the use of a 12/spl times/12 SCM power supply distribution model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.
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