{"title":"VLSI互连工艺集成","authors":"T. Kikkawa","doi":"10.1109/ICSICT.1998.785781","DOIUrl":null,"url":null,"abstract":"This paper describes VLSI interconnect process integration with respect to ULSI scaling. Both resistivity and capacitance are key factors for materials used in the interconnect process integration. In order to reduce parasitic resistances of sub-quarter micron CMOS transistors, salicide technologies have been developed for gate and source/drain electrodes. Copper interconnects and low-k interlayer dielectrics, in conjunction with CMP planarization, have been developed to reduce RC delay for future scaled ULSIs.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"VLSI interconnect process integration\",\"authors\":\"T. Kikkawa\",\"doi\":\"10.1109/ICSICT.1998.785781\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes VLSI interconnect process integration with respect to ULSI scaling. Both resistivity and capacitance are key factors for materials used in the interconnect process integration. In order to reduce parasitic resistances of sub-quarter micron CMOS transistors, salicide technologies have been developed for gate and source/drain electrodes. Copper interconnects and low-k interlayer dielectrics, in conjunction with CMP planarization, have been developed to reduce RC delay for future scaled ULSIs.\",\"PeriodicalId\":286980,\"journal\":{\"name\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1998.785781\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.785781","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes VLSI interconnect process integration with respect to ULSI scaling. Both resistivity and capacitance are key factors for materials used in the interconnect process integration. In order to reduce parasitic resistances of sub-quarter micron CMOS transistors, salicide technologies have been developed for gate and source/drain electrodes. Copper interconnects and low-k interlayer dielectrics, in conjunction with CMP planarization, have been developed to reduce RC delay for future scaled ULSIs.
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