{"title":"一种新型的高性能SIMD 54位乘法阵列","authors":"Zhao Lv, Shuming Chen, Yaohua Wang","doi":"10.1109/ICAM.2017.8242180","DOIUrl":null,"url":null,"abstract":"We present a novel SIMD multiply array for fixed-point and floating-point multiplication. To be concrete, the array supports one 54 (unsigned), one 32 or four 16 bits (signed/unsigned) operation. Based on the enhanced booth decode algorithm, the time overhead of the multiplications is reduced. The proposed intermediate result reuse strategy can reduce area overhead of the SIMD multiply array. The synthesize result shows the area can be reduced by 37% compared with the multiply without the reuse architecture.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A novel high performance SIMD 54-bit multiply array\",\"authors\":\"Zhao Lv, Shuming Chen, Yaohua Wang\",\"doi\":\"10.1109/ICAM.2017.8242180\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a novel SIMD multiply array for fixed-point and floating-point multiplication. To be concrete, the array supports one 54 (unsigned), one 32 or four 16 bits (signed/unsigned) operation. Based on the enhanced booth decode algorithm, the time overhead of the multiplications is reduced. The proposed intermediate result reuse strategy can reduce area overhead of the SIMD multiply array. The synthesize result shows the area can be reduced by 37% compared with the multiply without the reuse architecture.\",\"PeriodicalId\":117801,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAM.2017.8242180\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242180","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel high performance SIMD 54-bit multiply array
We present a novel SIMD multiply array for fixed-point and floating-point multiplication. To be concrete, the array supports one 54 (unsigned), one 32 or four 16 bits (signed/unsigned) operation. Based on the enhanced booth decode algorithm, the time overhead of the multiplications is reduced. The proposed intermediate result reuse strategy can reduce area overhead of the SIMD multiply array. The synthesize result shows the area can be reduced by 37% compared with the multiply without the reuse architecture.
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