用于ULSI倒装芯片技术的电镀碰撞工艺开发

R. Kiumi, J. Yoshioka, F. Kuriyama, N. Saito, M. Shimoyama
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引用次数: 10

摘要

对于倒装芯片封装应用,由于芯片电路密度、操作速度和性能的提高,需要在LSI晶圆上采用精细的节距凹凸工艺。电镀工艺适合于制作细节距凸点,沉积速度快,可靠性高。与此同时,电子设备和组件的无铅工艺也需要解决环境问题。此外,高速碰撞工艺必须开发大规模生产,低成本,小占地面积和高吞吐量。Ebara已经开发出了在硅晶片上以更高沉积速率电镀共晶锡铅焊料、高铅焊料、无铅焊料和铜螺柱凸点的电镀技术。凸起被制成柱状或蘑菇型使用抗蚀剂电镀掩膜,如负,正旋转,和干膜光抗蚀剂。结果表明,Ebara的工艺适合批量生产,凹凸几何形状控制良好。
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Process development of electroplate bumping for ULSI flip chip technology
For flip-chip packaging applications, a fine pitch bump process on LSI wafers is required due to increased chip circuit density, operating speed, and performance. Plating process is suitable for making the fine pitch bumps with high-speed deposition and high reliability. At the same time, lead-free processes, for electronic devices and components, are required to address environmental concerns. Also, high-speed bumping processes have to be developed for mass production, low cost, small footprint, and high throughput. Ebara has developed electroplating technologies for eutectic Sn-Pb solder, high lead solder, lead-free solder, and copper stud bumps on silicon wafers with higher deposition rates. The bumps were fabricated as column or mushroom type using resist plating masks, such as negative, positive spin-on, and dry film photo resists. The results show that Ebara's processes are suitable for mass production, with well-controlled bump geometry.
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