晶片与异质集成的晶圆间杂化键合:晶圆尺寸效应评估-小晶圆应用

Guilian Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, Thomas Workman, C. Uzoh, Bongsub Lee, K.M. Bang, Gabe Guevara
{"title":"晶片与异质集成的晶圆间杂化键合:晶圆尺寸效应评估-小晶圆应用","authors":"Guilian Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, Thomas Workman, C. Uzoh, Bongsub Lee, K.M. Bang, Gabe Guevara","doi":"10.1109/ectc51906.2022.00310","DOIUrl":null,"url":null,"abstract":"The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding, is a platform technology that offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. DBI wafer to wafer (W2W) bonding has been in high volume production since 2015. Advancement in D2W hybrid bonding technology in recent years has enabled recent adoption the technology by Sony [1]. AMD [2] and Intel [3]. The DBI Ultra D2W technology offers die-on-tape processing with bonding speeds comparable to mass reflow flip chip assembly. The bonding takes place at room temperature in an ambient environment in a class 1000 cleanroom. A low temperature batch anneal following bonding creates a solid Cu-Cu connection with no solder and no underfill.The value of the DBI Ultra technology can be realized in diverse products ranging from very small die to reticle-size large die. Applications such as RF, sensors and microcontrollers are in the small die domain, while GPUs and FPGAs require bonding of very large die. Ultimate SoC disaggregation implementations may include D2W bonding of mid-large sized memory die (e.g. SRAM in V-Cache) as well as ultra-small die for analog functionalities. In this paper, we present the results of D2W bonding development in die size ranging from 0.4x0.4mm to 3.2x3.0mm. The module build process includes dicing, die preparation on tape, and direct pick & place from a tape frame. The bonding quality is characterized with C-mode scanning acoustic microscopy (CSAM) and cross-section microscopy analysis.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects Evaluation-Small Die Applications\",\"authors\":\"Guilian Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, Thomas Workman, C. Uzoh, Bongsub Lee, K.M. Bang, Gabe Guevara\",\"doi\":\"10.1109/ectc51906.2022.00310\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding, is a platform technology that offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. DBI wafer to wafer (W2W) bonding has been in high volume production since 2015. Advancement in D2W hybrid bonding technology in recent years has enabled recent adoption the technology by Sony [1]. AMD [2] and Intel [3]. The DBI Ultra D2W technology offers die-on-tape processing with bonding speeds comparable to mass reflow flip chip assembly. The bonding takes place at room temperature in an ambient environment in a class 1000 cleanroom. A low temperature batch anneal following bonding creates a solid Cu-Cu connection with no solder and no underfill.The value of the DBI Ultra technology can be realized in diverse products ranging from very small die to reticle-size large die. Applications such as RF, sensors and microcontrollers are in the small die domain, while GPUs and FPGAs require bonding of very large die. Ultimate SoC disaggregation implementations may include D2W bonding of mid-large sized memory die (e.g. SRAM in V-Cache) as well as ultra-small die for analog functionalities. In this paper, we present the results of D2W bonding development in die size ranging from 0.4x0.4mm to 3.2x3.0mm. The module build process includes dicing, die preparation on tape, and direct pick & place from a tape frame. The bonding quality is characterized with C-mode scanning acoustic microscopy (CSAM) and cross-section microscopy analysis.\",\"PeriodicalId\":139520,\"journal\":{\"name\":\"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ectc51906.2022.00310\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ectc51906.2022.00310","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

直接键合互连(DBI®)超技术是一种模对晶圆(D2W)和模对模(D2D)混合键合技术,是一种平台技术,通过室温键合和低温退火提供密封的固体Cu-Cu互连。自2015年以来,DBI晶对晶(W2W)键合一直处于大批量生产状态。近年来D2W混合键合技术的进步使索尼最近采用了该技术[1]。AMD[2]和Intel[3]。DBI Ultra D2W技术提供带上模处理,键合速度可与大规模回流倒装芯片组装相媲美。粘接在1000级洁净室的室温环境中进行。低温批量退火后的键合创建一个坚实的Cu-Cu连接,没有焊料,没有底填充。DBI Ultra技术的价值可以在各种产品中实现,从非常小的模具到网线大小的大模具。RF、传感器和微控制器等应用属于小芯片领域,而gpu和fpga则需要绑定非常大的芯片。最终的SoC分解实现可能包括大中型内存芯片(例如V-Cache中的SRAM)的D2W键合以及用于模拟功能的超小型芯片。在本文中,我们展示了D2W键合在模具尺寸范围从0.4 × 0.4mm到3.2 × 3.0mm的结果。模块构建过程包括切割,在磁带上准备模具,以及从磁带框架直接拾取和放置。用c型扫描声学显微镜(CSAM)和截面显微镜分析表征了键合质量。
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Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects Evaluation-Small Die Applications
The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding, is a platform technology that offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. DBI wafer to wafer (W2W) bonding has been in high volume production since 2015. Advancement in D2W hybrid bonding technology in recent years has enabled recent adoption the technology by Sony [1]. AMD [2] and Intel [3]. The DBI Ultra D2W technology offers die-on-tape processing with bonding speeds comparable to mass reflow flip chip assembly. The bonding takes place at room temperature in an ambient environment in a class 1000 cleanroom. A low temperature batch anneal following bonding creates a solid Cu-Cu connection with no solder and no underfill.The value of the DBI Ultra technology can be realized in diverse products ranging from very small die to reticle-size large die. Applications such as RF, sensors and microcontrollers are in the small die domain, while GPUs and FPGAs require bonding of very large die. Ultimate SoC disaggregation implementations may include D2W bonding of mid-large sized memory die (e.g. SRAM in V-Cache) as well as ultra-small die for analog functionalities. In this paper, we present the results of D2W bonding development in die size ranging from 0.4x0.4mm to 3.2x3.0mm. The module build process includes dicing, die preparation on tape, and direct pick & place from a tape frame. The bonding quality is characterized with C-mode scanning acoustic microscopy (CSAM) and cross-section microscopy analysis.
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