{"title":"通过晶圆级排列晶圆键合实现三维集成","authors":"V. Dragoi, J. Burggraf, F. Kurz, B. Rebhan","doi":"10.1109/SMICND.2015.7355203","DOIUrl":null,"url":null,"abstract":"Wafer bonding is an attractive technology enabling manufacturing of complex wafer-level 3D architectures. The continuous demand for device size shrinking and performance improvement pushed for the development of new manufacturing technologies. This work reviews the main challenging raised for the wafer bonding processes and presents new developments in the aligned wafer bonding processes.","PeriodicalId":325576,"journal":{"name":"2015 International Semiconductor Conference (CAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"3D integration by wafer-level aligned wafer bonding\",\"authors\":\"V. Dragoi, J. Burggraf, F. Kurz, B. Rebhan\",\"doi\":\"10.1109/SMICND.2015.7355203\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Wafer bonding is an attractive technology enabling manufacturing of complex wafer-level 3D architectures. The continuous demand for device size shrinking and performance improvement pushed for the development of new manufacturing technologies. This work reviews the main challenging raised for the wafer bonding processes and presents new developments in the aligned wafer bonding processes.\",\"PeriodicalId\":325576,\"journal\":{\"name\":\"2015 International Semiconductor Conference (CAS)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Semiconductor Conference (CAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.2015.7355203\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Semiconductor Conference (CAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.2015.7355203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
3D integration by wafer-level aligned wafer bonding
Wafer bonding is an attractive technology enabling manufacturing of complex wafer-level 3D architectures. The continuous demand for device size shrinking and performance improvement pushed for the development of new manufacturing technologies. This work reviews the main challenging raised for the wafer bonding processes and presents new developments in the aligned wafer bonding processes.