{"title":"基于集群的多级分层FPGA布局","authors":"Hui Dai, Qiang Zhou, Jinian Bian, Yanhua Wang","doi":"10.1109/ICSICT.2008.4735045","DOIUrl":null,"url":null,"abstract":"In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"220 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Cluster-based Placement for multilevel hierarchical FPGA\",\"authors\":\"Hui Dai, Qiang Zhou, Jinian Bian, Yanhua Wang\",\"doi\":\"10.1109/ICSICT.2008.4735045\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.\",\"PeriodicalId\":436457,\"journal\":{\"name\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"volume\":\"220 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.2008.4735045\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4735045","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Cluster-based Placement for multilevel hierarchical FPGA
In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.
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