微处理器的性能测试用例生成

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI:10.1109/VTEST.1998.670849

P. Bose

{"title":"微处理器的性能测试用例生成","authors":"P. Bose","doi":"10.1109/VTEST.1998.670849","DOIUrl":null,"url":null,"abstract":"We describe a systematic methodology for generating performance test cases for current generation microprocessors. Such rest cases are used for: (a) validating the expected pipeline flow behavior and timing; and, (b) detecting and diagnosing performance bugs in the design. We cite examples of application to a real, superscalar processor in pre- and post-silicon stages of development.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Performance test case generation for microprocessors\",\"authors\":\"P. Bose\",\"doi\":\"10.1109/VTEST.1998.670849\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a systematic methodology for generating performance test cases for current generation microprocessors. Such rest cases are used for: (a) validating the expected pipeline flow behavior and timing; and, (b) detecting and diagnosing performance bugs in the design. We cite examples of application to a real, superscalar processor in pre- and post-silicon stages of development.\",\"PeriodicalId\":128521,\"journal\":{\"name\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1998.670849\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1998.670849","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 18

摘要

我们描述了为当前一代微处理器生成性能测试用例的系统方法。这些剩余情况用于:(a)验证预期的管道流动行为和时间;(b)检测和诊断设计中的性能缺陷。我们列举了应用于实际的、在硅前和硅后发展阶段的超标量处理器的例子。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Performance test case generation for microprocessors

We describe a systematic methodology for generating performance test cases for current generation microprocessors. Such rest cases are used for: (a) validating the expected pipeline flow behavior and timing; and, (b) detecting and diagnosing performance bugs in the design. We cite examples of application to a real, superscalar processor in pre- and post-silicon stages of development.

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Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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