Functional Demonstration of < 0.4-pJ/bit, 9.8 μm Fine-Pitch Dielet-to-Dielet Links for Advanced Packaging using Silicon Interconnect Fabric

This work successfully demonstrates functional multi-dielet communication on Silicon Interconnect Fabric (Si-IF) platform using Simple Universal Parallel intERface for CHIPS or SuperCHIPS interface at < 10 μm bump pitch. SuperCHIPS interfaces were implemented in two different functional assemblies for the first time at < 10 μm pitch. The first assembly is used to study the variation in SuperCHIPS link latency and energy/bit with respect to frequency and operating voltage (VDD) scaling. At nominal voltage (VDD) of 0.8V, the measured link data rate is 3 Gbps/link with < 20 ps latency. The second assembly consists of 2×2 dielets on Si-IF, which communicate using multiple SuperCHIPS interfaces mediated by a Streaming Near Range-10pm (SNR-10) channel and protocol. The measured inter-dielet bandwidth of the 2×2 system is 492.8 Gbps.