{"title":"1GHz信号带宽4通道i /Q多相fft滤波器组","authors":"Hundo Shin, R. Harjani","doi":"10.1109/ESSCIRC.2016.7598315","DOIUrl":null,"url":null,"abstract":"This paper presents a prototype analog 4-channel-I/Q polyphase-FFT filter bank (PFFB) using passive switched capacitor circuits to channelize wideband signals. Like FFTs, the proposed PFFB shares computations for low power. The PFFB allows for a longer “effective window length” than is possible in a standard FFT. This characteristic of the PFFB maintains a narrow main-lobe bandwidth combined with low side-lobe amplitudes. The passive switched capacitor structure enables high linearity and low power implementation. The measured performance of the prototype fabricated in TSMC 65nm CMOS shows >40dB side-lobe suppression, +25dBm IIP3, and 208μVrms integrated output noise for all channels at 1GS/s operation. The total power consumption for the PFFB (8-channels total) is 34.6mW (34.6pJ/conv).","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"204 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bank\",\"authors\":\"Hundo Shin, R. Harjani\",\"doi\":\"10.1109/ESSCIRC.2016.7598315\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a prototype analog 4-channel-I/Q polyphase-FFT filter bank (PFFB) using passive switched capacitor circuits to channelize wideband signals. Like FFTs, the proposed PFFB shares computations for low power. The PFFB allows for a longer “effective window length” than is possible in a standard FFT. This characteristic of the PFFB maintains a narrow main-lobe bandwidth combined with low side-lobe amplitudes. The passive switched capacitor structure enables high linearity and low power implementation. The measured performance of the prototype fabricated in TSMC 65nm CMOS shows >40dB side-lobe suppression, +25dBm IIP3, and 208μVrms integrated output noise for all channels at 1GS/s operation. The total power consumption for the PFFB (8-channels total) is 34.6mW (34.6pJ/conv).\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"204 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598315\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598315","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bank
This paper presents a prototype analog 4-channel-I/Q polyphase-FFT filter bank (PFFB) using passive switched capacitor circuits to channelize wideband signals. Like FFTs, the proposed PFFB shares computations for low power. The PFFB allows for a longer “effective window length” than is possible in a standard FFT. This characteristic of the PFFB maintains a narrow main-lobe bandwidth combined with low side-lobe amplitudes. The passive switched capacitor structure enables high linearity and low power implementation. The measured performance of the prototype fabricated in TSMC 65nm CMOS shows >40dB side-lobe suppression, +25dBm IIP3, and 208μVrms integrated output noise for all channels at 1GS/s operation. The total power consumption for the PFFB (8-channels total) is 34.6mW (34.6pJ/conv).