{"title":"主动漏源/源应力问题导致40nm甜甜圈扫描失败","authors":"Wen Bin Low, James Lai, Liang Chun Sung","doi":"10.1109/ASMC.2019.8791778","DOIUrl":null,"url":null,"abstract":"40nm devices suffered donut scan bin failure and result in yield loss, and these failures are particularly occurs in devices with high-Vt nMOSFET (HVTN) cores. These failures are mainly caused by combination of two factors: HVTN manufacturing process and Active (RX) layer design. Based on studies, reduce the RX CD and introduction of N2 implant in HVTN process step help to reduce yield loss.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"40nm Donut Scan Failed Induced by Active Drain/Source Stress Issue\",\"authors\":\"Wen Bin Low, James Lai, Liang Chun Sung\",\"doi\":\"10.1109/ASMC.2019.8791778\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"40nm devices suffered donut scan bin failure and result in yield loss, and these failures are particularly occurs in devices with high-Vt nMOSFET (HVTN) cores. These failures are mainly caused by combination of two factors: HVTN manufacturing process and Active (RX) layer design. Based on studies, reduce the RX CD and introduction of N2 implant in HVTN process step help to reduce yield loss.\",\"PeriodicalId\":287541,\"journal\":{\"name\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2019.8791778\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2019.8791778","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
40nm Donut Scan Failed Induced by Active Drain/Source Stress Issue
40nm devices suffered donut scan bin failure and result in yield loss, and these failures are particularly occurs in devices with high-Vt nMOSFET (HVTN) cores. These failures are mainly caused by combination of two factors: HVTN manufacturing process and Active (RX) layer design. Based on studies, reduce the RX CD and introduction of N2 implant in HVTN process step help to reduce yield loss.
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